Sequential Logic: Latches & Flip-Flops

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Clocks and synchronous circuits

A sequential circuit stores state, so its output depends on inputs and history. A clock is a periodic square wave with a period T, frequency f = 1/T, rising and falling edges and a duty cycle. In a synchronous circuit all state changes are coordinated by the clock, which makes timing predictable and design easier. In an asynchronous circuit, state can change as soon as an input changes.

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Latches

A latch is level-sensitive: its output can change while its enable is active. An SR latch is two cross-coupled NOR gates. S = 1 sets Q to 1, R = 1 resets it to 0, and S = R = 0 holds. S = R = 1 is invalid for the NOR version, because both outputs go to 0 and the result is unpredictable when the inputs are released. A gated latch adds an enable. A D latch uses one data input, D, which removes the invalid state: while enabled, Q follows D.

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Flip-flops

A flip-flop is edge-triggered: it samples its inputs only at a clock edge (rising or falling), so it changes state at one precise moment.

A level-triggered JK with J = K = 1 would keep toggling while the clock is high (race-around). A master-slave JK, built from two latches on opposite clock phases, avoids this.

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Master-slave JK flip-flop

A master-slave JK flip-flop chains two clocked SR latches so the circuit changes state only once per clock cycle, even when J = K = 1. The master latch is enabled while the clock is high and follows J and K; the slave latch is enabled while the clock is low (its clock input is the inverted clock) and simply copies whatever the master is holding. Because the master and slave are never active at the same time, the master's new output can't loop back through the slave and re-trigger itself — this is what removes the race-around problem of a plain level-triggered JK.

With J = K = 1: while the clock is high, the master toggles once to its new value and then sits still for the rest of the high phase, since it cannot see its own new output until the next clock cycle. When the clock falls, the slave copies that single new value through to Q. Net result: exactly one toggle per clock cycle.

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Characteristic and excitation tables

The characteristic table gives the next state from the inputs (used for analysis). The excitation table gives the inputs needed for a wanted transition (used for design).

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Timing

• Setup time: data must be stable this long before the clock edge.
• Hold time: data must stay stable this long after the edge.
• Propagation delay: time for a gate output to respond to an input.
• Clock-to-Q delay: time from the clock edge until Q changes.

Breaking setup or hold time can store the wrong value or leave the flip-flop in an in-between state.

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Timing (cont.)