Topic 11 of 13
Memory & Error Correction
How memory is organised, decoded and expanded, and how errors are detected and corrected.
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Before we start
Why this matters
When Voyager 1 beams a photo home from over 15 billion miles away and cosmic rays casually flip a few of its bits mid-flight, how does the picture still turn out fine?
Error-correcting codes let the receiver catch a flipped bit and quietly fix it, no “can you resend that?” across a round trip that takes over a day one-way. It's the same superpower that lets a scratched CD keep playing and your Wi-Fi survive the microwave reheating last night's leftovers. It all starts with memory organised into tidy, addressable rows and columns.
Outline
Topics in this chapter
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Concept 1 of 4
Memory organisation
Memory stores binary words at numbered addresses. It is described as words × bits per word: 1K × 8 means 1024 words of 8 bits. n address lines select 2n locations. Data lines carry the word to or from memory.
- Read: apply the address, enable the memory, activate read, and the word appears on the data lines.
- Write: apply address and data, enable the memory, activate write, and the word is stored.
10 address lines, 8 data lines: 1024 × 8 = 8192 bits = 1 KB
Concept 2 of 4
RAM: SRAM and DRAM
Random-access memory can be read and written at any address in the same time. SRAM uses bistable cells, needs no refresh and is fast, but its cost and size rule it out as a computer's main memory — it is used for the much smaller cache instead. DRAM stores charge in a capacitor, so it must be refreshed periodically, but it draws less power and packs more bits per chip, which is why it does the job of main memory. Both lose their contents without power.
Concept 3 of 4
Address decoding and expansion
A decoder turns address bits into a select line for a location or a chip. A chip select input enables only the chip being addressed. Many chips share one tri-state data bus, and only the selected chip drives it.
- Word expansion adds locations: extra high address bits feed a decoder that drives the chip selects.
- Bit expansion widens the word: chips share the address lines and their data lines side by side (two 4-bit chips make an 8-bit word).
A memory map lists which address range belongs to which device.
Concept 3 of 4
Address decoding and expansion (cont.)
Concept 4 of 4
Error detection and correction
A parity bit detects any single-bit error but cannot say which bit. A Hamming code places check bits at the power-of-two positions (1, 2, 4, …). Recomputing the checks after a read gives a syndrome, which is the position of a single wrong bit, so it can be flipped back. Adding one overall parity bit gives SEC-DED: single-error correction and double-error detection.
Truth tables
Truth tables (1 of 2)
Memory control table
| CS | R/W | Operation |
|---|---|---|
| 0 | X | Not selected (outputs Hi-Z) |
| 1 | Read | Word appears on the data lines |
| 1 | Write | Data lines are stored |
Hamming (7,4) syndrome
| s3 s2 s1 | Meaning |
|---|---|
| 000 | No error |
| 001 | Error in bit 1 (flip it back) |
| 010 | Error in bit 2 (flip it back) |
| 011 | Error in bit 3 (flip it back) |
| 100 | Error in bit 4 (flip it back) |
| 101 | Error in bit 5 (flip it back) |
| 110 | Error in bit 6 (flip it back) |
| 111 | Error in bit 7 (flip it back) |
Truth tables
Truth tables (2 of 2)
Hamming (7,4) check bits
| d1 | d2 | d3 | d4 | p1 | p2 | p3 |
|---|---|---|---|---|---|---|
| 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| 0 | 0 | 0 | 1 | 1 | 1 | 1 |
| 0 | 0 | 1 | 0 | 0 | 1 | 1 |
| 0 | 0 | 1 | 1 | 1 | 0 | 0 |
| 0 | 1 | 0 | 0 | 1 | 0 | 1 |
| 0 | 1 | 0 | 1 | 0 | 1 | 0 |
| 0 | 1 | 1 | 0 | 1 | 1 | 0 |
| 0 | 1 | 1 | 1 | 0 | 0 | 1 |
| 1 | 0 | 0 | 0 | 1 | 1 | 0 |
| 1 | 0 | 0 | 1 | 0 | 0 | 1 |
| 1 | 0 | 1 | 0 | 1 | 0 | 1 |
| 1 | 0 | 1 | 1 | 0 | 1 | 0 |
| 1 | 1 | 0 | 0 | 0 | 1 | 1 |
| 1 | 1 | 0 | 1 | 1 | 0 | 0 |
| 1 | 1 | 1 | 0 | 0 | 0 | 0 |
| 1 | 1 | 1 | 1 | 1 | 1 | 1 |
p1 = d1⊕d2⊕d4, p2 = d1⊕d3⊕d4, p3 = d2⊕d3⊕d4.
SEC-DED decision table (syndrome C, overall parity P)
| C | P | Meaning |
|---|---|---|
| 0 | 0 | No error |
| ≠0 | 1 | Single error — correctable (flip the bit C points to) |
| ≠0 | 0 | Double error — detected, not correctable |
| 0 | 1 | Error in the overall parity bit itself |
C is the Hamming syndrome over the original check bits; P is the parity over all 13 bits, including the added overall parity bit.
Interactive
Demo: memory workbench
Worked example 1 of 3
Worked example 1
Show the solution
- 212 = 4096 locations.
- 2K × 8 = 2048 × 8 = 16384 bits = 2 KB.
Worked example 2 of 3
Worked example 2
Show the solution
- Chips needed: 4K / 1K = 4.
- Address lines: 12. The low 10 go to every chip. The top 2 feed a 2-to-4 decoder that drives the four chip selects.
Worked example 3 of 3
Worked example 3
Show the solution
- XOR the 12 bits: 0⊕0⊕1⊕1⊕1⊕0⊕0⊕1⊕0⊕1⊕0⊕0 = 1, so P13 = 1.
- 13-bit SEC-DED word: 001110010100 with P13 appended = 0011100101001.
- C ≠ 0 and P = 1 means a single bit is wrong. Look up C in the syndrome table and flip that bit — the error is correctable.
Practice
Practice (1 of 2)
Try each one on paper first, then check your answer.
Show the answer
Show the answer
Show the answer
Practice
Practice (2 of 2)
Try each one on paper first, then check your answer.
Show the answer
Show the answer
Build an address decoder from gates, or a one-bit storage cell from latches.
Gate ForgeA free circuit simulator — place and wire gates, generate truth tables and timing diagrams, and work through 90+ guided problems.Check yourself
Quiz
Summary
Summary
- n address lines select 2n locations.
- SRAM: fast, no refresh. DRAM: dense, needs refresh.
- Decoders and chip selects choose the active device.
- Word expansion adds locations, bit expansion adds width.
- SEC-DED corrects one error and detects two.