Main Memory

Before we start

Why this matters

Chapter 9 · Lectures 9–10

Outline

Select a topic to jump to the slide that explains it.

1. Background
2. Contiguous memory allocation
3. Paging
4. Structure of the page table
5. Swapping

Background

Background

• Program must be brought (from disk) into memory and placed within a process for it to be run
• Main memory and registers are only storage CPU can access directly
• Memory unit only sees a stream of:
  • addresses + read requests, or
  • address + data and write requests
• Register access is done in one CPU clock (or less)
• Main memory can take many cycles, causing a stall
• Cache sits between main memory and CPU registers
• Protection of memory required to ensure correct operation

Background

Protection

• Need to ensure that a process can access only those addresses in its address space.
• We can provide this protection by using a pair of base and limit registers that define the logical address space of a process

Background

Protection (cont.)

Background

Hardware address protection

Background

Hardware address protection (cont.)

• CPU must check every memory access generated in user mode to be sure it is between base and limit for that user
• The instructions to load the base and limit registers are privileged

Interactive

Check an address

Contiguous memory allocation

Contiguous allocation

• Main memory must support both OS and user processes
• Limited resource, must allocate efficiently
• Contiguous allocation is one early method
• Main memory usually into two partitions:
  • Resident operating system, usually held in low memory with interrupt vector
  • User processes then held in high memory
  • Each process contained in single contiguous section of memory

Contiguous memory allocation

Contiguous allocation (cont.)

• Relocation registers used to protect user processes from each other, and from changing operating-system code and data
  • Base register contains value of smallest physical address
  • Limit register contains range of logical addresses – each logical address must be less than the limit register
  • MMU maps logical address dynamically
  • Can then allow actions such as kernel code being transient and kernel changing size

Contiguous memory allocation

Variable partition

• Multiple-partition allocation
  • Degree of multiprogramming limited by number of partitions
  • Variable-partition sizes for efficiency (sized to a given process’ needs)
  • Hole – block of available memory; holes of various size are scattered throughout memory
  • When a process arrives, it is allocated memory from a hole large enough to accommodate it
  • Process exiting frees its partition, adjacent free partitions combined
  • Operating system maintains information about: a) allocated partitions b) free partitions (hole)

Contiguous memory allocation

Dynamic storage-allocation problem

Interactive

First-fit, best-fit, worst-fit

Paging

Paging

• Physical address space of a process can be noncontiguous; process is allocated physical memory whenever the latter is available
  • Avoids external fragmentation
  • Avoids problem of varying sized memory chunks
• Divide physical memory into fixed-sized blocks called frames
  • Size is power of 2, between 512 bytes and 16 Mbytes
• Divide logical memory into blocks of same size called pages
• Keep track of all free frames
• To run a program of size N pages, need to find N free frames and load program
• Set up a page table to translate logical to physical addresses
• Backing store likewise split into pages
• Still have internal fragmentation

Paging

Address translation scheme

• Address generated by CPU is divided into:
  • Page number (p) – used as an index into a page table which contains base address of each page in physical memory
  • Page offset (d) – combined with base address to define the physical memory address that is sent to the memory unit
  • For given logical address space 2^m and page size 2ⁿ

Paging

Address translation scheme (cont.)

Paging

Paging model of logical and physical memory

Interactive

Paging example

Logical address: n = 2 and m = 4. Using a page size of 4 bytes and a physical memory of 32 bytes (8 pages).

Interactive

Paging example (cont.)

Interactive

Translate any address

Code and output

Address translation in C

#include <stdio.h>

#define PAGE_SIZE 4096                       /* 2^12 bytes */
int page_table[] = {5, 9, 2, 7, 1, 0, 3, 8}; /* frame of page 0, 1, 2, ... */

int main(void)
{
    unsigned addr[] = {0x0000, 0x1A3C, 0x2710, 0x7FFF, 0x9000};

    for (int i = 0; i < 5; i++) {
        unsigned p = addr[i] / PAGE_SIZE;    /* page number = high bits */
        unsigned d = addr[i] % PAGE_SIZE;    /* offset = low 12 bits    */
        if (p >= sizeof page_table / sizeof page_table[0]) {
            printf("0x%04X: p = %u -> invalid page, trap!\n", addr[i], p);
            continue;

Code and output

Address translation in C (cont.)

        }
        unsigned f = page_table[p];
        printf("0x%04X: p = %u, d = 0x%03X -> frame %u -> physical 0x%05X\n",
               addr[i], p, d, f, f * PAGE_SIZE + d);
    }
    return 0;
}

$ gcc xlate.c -o xlate -pthread && ./xlate
0x0000: p = 0, d = 0x000 -> frame 5 -> physical 0x05000
0x1A3C: p = 1, d = 0xA3C -> frame 9 -> physical 0x09A3C
0x2710: p = 2, d = 0x710 -> frame 2 -> physical 0x02710
0x7FFF: p = 7, d = 0xFFF -> frame 8 -> physical 0x08FFF
0x9000: p = 9 -> invalid page, trap!

The page number is the address divided by the page size (its high bits); the offset is the remainder (its low 12 bits). Page 9 is beyond the 8-entry page table, so the hardware would trap.

Paging

Paging – calculating internal fragmentation

Paging

Free frames

Paging

Implementation of page table

• Page table is kept in main memory
  • Page-table base register (PTBR) points to the page table
  • Page-table length register (PTLR) indicates size of the page table
• In this scheme every data/instruction access requires two memory accesses
  • One for the page table and one for the data / instruction
• The two-memory access problem can be solved by the use of a special fast-lookup hardware cache called translation look-aside buffers (TLBs) (also called associative memory).

Paging

Translation look-aside buffer

• Some TLBs store address-space identifiers (ASIDs) in each TLB entry – uniquely identifies each process to provide address-space protection for that process
  • Otherwise need to flush at every context switch
• TLBs typically small (64 to 1,024 entries)
• On a TLB miss, value is loaded into the TLB for faster access next time
  • Replacement policies must be considered
  • Some entries can be wired down for permanent fast access

Paging

Translation look-aside buffer (cont.)

Paging

Effective access time

• Hit ratio – percentage of times that a page number is found in the TLB
• An 80% hit ratio means that we find the desired page number in the TLB 80% of the time.
• Suppose that 10 nanoseconds to access memory.
  • If we find the desired page in TLB then a mapped-memory access takes 10 ns
  • Otherwise we need two memory accesses so it is 20 ns

implying 20% slowdown in access time. Consider a more realistic hit ratio of 99%:

Paging

Effective access time (cont.)

implying only 1% slowdown in access time.

Animated

Translating one address, animated

Interactive

TLB simulator

Paging

Memory protection

• Memory protection implemented by associating protection bit with each frame to indicate if read-only or read-write access is allowed
  • Can also add more bits to indicate page execute-only, and so on
• Valid-invalid bit attached to each entry in the page table:
  • “valid” indicates that the associated page is in the process’ logical address space, and is thus a legal page
  • “invalid” indicates that the page is not in the process’ logical address space
  • Or use page-table length register (PTLR)
• Any violations result in a trap to the kernel

Paging

Memory protection (cont.)

Paging

Shared pages

• Shared code
  • One copy of read-only (reentrant) code shared among processes (i.e., text editors, compilers, window systems)
  • Similar to multiple threads sharing the same process space
  • Also useful for interprocess communication if sharing of read-write pages is allowed
• Private code and data
  • Each process keeps a separate copy of the code and data
  • The pages for the private code and data can appear anywhere in the logical address space

Paging

Shared pages (cont.)

Structure of the page table

Structure of the page table

• Memory structures for paging can get huge using straight-forward methods
  • Consider a 32-bit logical address space as on modern computers
  • Page size of 4 KB (2¹²)
  • Page table would have 1 million entries (2³² / 2¹²)
  • If each entry is 4 bytes → each process 4 MB of physical address space for the page table alone
    • Don’t want to allocate that contiguously in main memory
  • One simple solution is to divide the page table into smaller units
    • Hierarchical paging
    • Hashed page tables
    • Inverted page tables

Structure of the page table

Hierarchical page tables

• Break up the logical address space into multiple page tables
• A simple technique is a two-level page table
• We then page the page table

Structure of the page table

Hierarchical page tables (cont.)

Structure of the page table

Two-level paging example

• A logical address (on 32-bit machine with 4K page size) is divided into:
  • a page number consisting of 20 bits
  • a page offset consisting of 12 bits
• Since the page table is paged, the page number is further divided into:
  • a 10-bit page number
  • a 10-bit page offset
• Thus, a logical address is as follows: where p₁ is an index into the outer page table, and p₂ is the displacement within the page of the inner page table
• Known as forward-mapped page table

Structure of the page table

Two-level paging example (cont.)

Interactive

Split an address

Structure of the page table

64-bit logical address space

• Even two-level paging scheme not sufficient
• If page size is 4 KB (2¹²)
  • Then page table has 2⁵² entries
  • If two level scheme, inner page tables could be 2¹⁰ 4-byte entries
  • Outer page table has 2⁴² entries or 2⁴⁴ bytes
  • One solution is to add a 2nd outer page table
  • But in the following example the 2nd outer page table is still 2³⁴ bytes in size
    • And possibly 4 memory accesses to get to one physical memory location

Structure of the page table

64-bit logical address space (cont.)

Structure of the page table

Hashed page tables

• Common in address spaces > 32 bits
• The virtual page number is hashed into a page table
  • This page table contains a chain of elements hashing to the same location
• Each element contains (1) the virtual page number (2) the value of the mapped page frame (3) a pointer to the next element
• Virtual page numbers are compared in this chain searching for a match
  • If a match is found, the corresponding physical frame is extracted
• Variation for 64-bit addresses is clustered page tables
  • Similar to hashed but each entry refers to several pages (such as 16) rather than 1
  • Especially useful for sparse address spaces (where memory references are non-contiguous and scattered)

Structure of the page table

Hashed page tables (cont.)

Structure of the page table

Inverted page table

• Rather than each process having a page table and keeping track of all possible logical pages, track all physical pages
• One entry for each real page of memory
• Entry consists of the virtual address of the page stored in that real memory location, with information about the process that owns that page
• Decreases memory needed to store each page table, but increases time needed to search the table when a page reference occurs
• Use hash table to limit the search to one — or at most a few — page-table entries
  • TLB can accelerate access
• But how to implement shared memory?
  • One mapping of a virtual address to the shared physical address

Structure of the page table

Inverted page table (cont.)

Swapping

Swapping

• A process can be swapped temporarily out of memory to a backing store, and then brought back into memory for continued execution
  • Total physical memory space of processes can exceed physical memory
• Backing store – fast disk large enough to accommodate copies of all memory images for all users; must provide direct access to these memory images
• Roll out, roll in – swapping variant used for priority-based scheduling algorithms; lower-priority process is swapped out so higher-priority process can be loaded and executed
• Major part of swap time is transfer time; total transfer time is directly proportional to the amount of memory swapped
• System maintains a ready queue of ready-to-run processes which have memory images on disk

Swapping

Swapping (cont.)

• Does the swapped out process need to swap back in to same physical addresses?
• Depends on address binding method
  • Plus consider pending I/O to / from process memory space
• Modified versions of swapping are found on many systems (i.e., UNIX, Linux, and Windows)
  • Swapping normally disabled
  • Started if more than threshold amount of memory allocated
  • Disabled again once memory demand reduced below threshold

Swapping

Swapping (cont.)

Swapping

Context switch time including swapping

• If next process to be put on CPU is not in memory, need to swap out a process and swap in target process
• Context switch time can then be very high
• 100 MB process swapping to hard disk with transfer rate of 50 MB/sec
  • Swap out time of 2000 ms
  • Plus swap in of same sized process
  • Total context switch swapping component time of 4000 ms (4 seconds)

Swapping

Context switch time including swapping (cont.)

• Can reduce if reduce size of memory swapped – by knowing how much memory really being used
  • System calls to inform OS of memory use via request_memory() and release_memory()

Swapping

Context switch time and swapping (cont.)

• Other constraints as well on swapping
  • Pending I/O – can’t swap out as I/O would occur to wrong process
  • Or always transfer I/O to kernel space, then to I/O device
    • Known as double buffering, adds overhead
• Standard swapping not used in modern operating systems
  • But modified version common
    • Swap only when free memory extremely low

Swapping

Swapping on mobile systems

• Not typically supported
  • Flash memory based
    • Small amount of space
    • Limited number of write cycles
    • Poor throughput between flash memory and CPU on mobile platform
• Instead use other methods to free memory if low
  • iOS asks apps to voluntarily relinquish allocated memory
    • Read-only data thrown out and reloaded from flash if needed
    • Failure to free can result in termination
  • Android terminates apps if low free memory, but first writes application state to flash for fast restart
  • Both OSes support paging as discussed below

Swapping

Swapping with paging

Worked example 1 of 3

Worked example 1

Worked example 2 of 3

Worked example 2

Worked example 3 of 3

Worked example 3

Practice

Practice (1 of 2)

Try each one on paper first, then check your answer.

Practice

Practice (2 of 2)

Try each one on paper first, then check your answer.

Check yourself

Quiz

Resources

Further learning

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Summary · End of Chapter 9

Summary

• Base and limit registers, checked by hardware on every user-mode access, protect each process’s memory.
• Contiguous allocation places each process in one hole: first-fit, best-fit or worst-fit; it suffers external fragmentation (50-percent rule).
• Paging splits logical memory into pages and physical memory into frames; the page table maps page number p to frame f, and the offset d is unchanged.
• Paging removes external fragmentation but keeps internal fragmentation (on average half a page).
• A TLB caches page-table entries: EAT = hit × m + miss × 2m; valid-invalid and protection bits catch illegal accesses, and shared pages save memory.
• Large address spaces use hierarchical, hashed or inverted page tables; swapping moves processes or pages to a backing store.