Practice
Drills for quick repetition, and every topic’s practice problems in one place.
Gate Forge
Your circuit simulator: place and wire gates, generate truth tables and timing diagrams, and work through 90+ guided problems on adders, multiplexers, flip-flops and counters.
Problems by topic
1. Introduction to Digital Logic
1. Classify each as combinational or sequential: a 4-bit adder, a counter, a decoder, a register.
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Adder and decoder are combinational. Counter and register are sequential because they store state.
2. Write the truth table of a 2-input AND gate.
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00 → 0, 01 → 0, 10 → 0, 11 → 1.
3. Give two reasons digital systems tolerate noise better than analog ones.
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Signals are read against thresholds, so small deviations decode to the same bit, and a noisy signal can be regenerated to clean levels.
4. How many bits are needed to label 100 different items?
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7 bits, because 26 = 64 is too small and 27 = 128 is enough.
2. Number Systems & Binary Codes
1. Convert 101101₂ to decimal.
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45
2. Find the 2’s complement of 00101101.
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11010011 (invert to 11010010, add 1).
3. Write 59 in BCD.
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0101 1001
4. Perform the BCD addition 8 + 5.
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0001 0011 (13)
5. Convert 1011 to Gray code.
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1110
6. Convert 11010110₂ to octal and hexadecimal.
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Octal: 011 010 110 = 326₈. Hex: 1101 0110 = D6₁₆.
3. Boolean Algebra & Logic Gates
1. Simplify A + AB.
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A, by absorption.
2. Apply DeMorgan to (AB + C)′.
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(A′ + B′)C′
3. A 2-input function is 1 only for inputs 01 and 10. Write its canonical SOP and POS.
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SOP: A′B + AB′ = Σm(1,2). POS: (A+B)(A′+B′) = ΠM(0,3). This is XOR.
4. Write the dual of A + BC′.
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A(B + C′)
4. Universal Gates & Karnaugh Maps
1. Build NOT, AND and OR using only NAND gates.
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NOT: tie both inputs. AND: NAND then NOT. OR: NAND(A′, B′) where each input is first inverted by a NAND.
2. Build NOT, OR and AND using only NOR gates.
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NOT: tie both inputs. OR: NOR then NOT. AND: NOR(A′, B′).
3. Simplify F(A,B,C) = Σm(0,1,2,5,6,7).
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A′B′ + BC′ + AC (or A′C′ + B′C + AB). Both have three terms.
4. Simplify F(A,B,C,D) = Σm(1,3,5,7,9) + d(11,13,15).
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D. Every odd cell is 1 or X, so one group of eight covers them.
5. Simplify F(A,B,C,D) = Σm(0,1,2,4,5,6,8,9,12,13,14).
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C′ + A′D′ + BD′
5. Combinational Logic & Arithmetic Circuits
1. Derive the half adder equations.
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S = A ⊕ B, C = AB.
2. How do you build a full adder from half adders?
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The first half adder adds A and B. The second adds that sum and Cin. OR the two carry outputs to get Cout.
3. Derive the half subtractor equations.
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D = A ⊕ B, Borrow = A′B.
4. Explain ripple-carry delay.
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Each stage must wait for the carry from the previous stage, so total delay is roughly n times the carry delay of one full adder.
5. Perform the BCD addition 7 + 8.
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0001 0101 (15).
6. Design a 1-bit magnitude comparator.
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G = AB′, E = A XNOR B, L = A′B.
6. Decoders, Encoders & Data Selectors
1. Design a 2-to-4 decoder.
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Y0 = A′B′, Y1 = A′B, Y2 = AB′, Y3 = AB (four AND gates and two inverters).
2. Design a 4-to-2 encoder.
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A = D2 + D3, B = D1 + D3 (assuming one active input).
3. Write the equation of a 2-to-1 MUX.
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Y = S′·I0 + S·I1
4. Explain priority encoding.
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When several inputs are 1, the encoder outputs the code of the highest-priority one, and a valid bit shows whether any input is active.
5. Compare MUX and DEMUX.
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MUX selects one of many inputs for one output. DEMUX routes one input to one of many outputs.
7. Sequential Logic: Latches & Flip-Flops
1. Explain the difference between a latch and a flip-flop.
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A latch is level-sensitive: it follows its inputs while enabled. A flip-flop is edge-triggered: it samples inputs only at a clock edge.
2. Draw an SR latch.
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Two NOR gates. The output of each feeds one input of the other. The free inputs are R (for Q) and S (for Q′).
3. Explain D flip-flop operation.
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At the active clock edge, Q takes the value of D. Between edges Q holds.
4. Compare JK and T flip-flops.
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A T flip-flop is a JK with J and K tied together. T = 0 holds, T = 1 toggles.
5. Explain rising-edge triggering.
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The flip-flop looks at its inputs only at the instant the clock goes from 0 to 1 and ignores changes at other times.
8. State Machines & Sequential Circuit Design
1. Convert a state diagram into a state table.
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For each state and each input value, write the next state and the output. One row per (state, input) pair.
2. How do you identify equivalent states?
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Compare rows: same outputs for every input, and next states that are the same or themselves equivalent.
3. How many flip-flops for 10 states?
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4
4. Design a 101 sequence detector.
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Use the simulator to get the state table and D equations, then build the circuit with D flip-flops in Gate Forge.
9. Counters
1. Design a 3-bit ripple counter.
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Three T flip-flops with T = 1. Clock the first, and connect Q′ of each stage to the clock of the next (for positive-edge flip-flops). Try the circuit below.
2. Compare ripple and synchronous counters.
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Ripple: clock passes stage to stage, simple, accumulating delay. Synchronous: common clock, faster, needs extra gates.
3. Design an up/down counter.
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Add a control input. For stage k use Tk = (Q0·…·Qk−1)·UP + (Q0′·…·Qk−1′)·DOWN, with T0 = 1.
4. How many flip-flops for a MOD-12 counter?
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4
5. Explain ring and Johnson counters.
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A ring counter circulates one 1 (n states). A Johnson counter feeds back the complement of the last stage (2n states).
10. Registers
1. Design a 4-bit SISO register.
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Four D flip-flops in a chain: Q of each feeds D of the next, one common clock. Try the shift register circuit.
2. Explain SIPO and PISO.
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SIPO takes serial data in and presents all bits in parallel. PISO loads all bits in parallel and shifts them out serially.
3. What is the purpose of Load?
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Load = 1 accepts new data at the clock edge. Load = 0 keeps the current value.
4. Demonstrate four right shifts.
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See the example above, or use the simulator.
5. Write RTL for register transfers.
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R2 ← R1, R1 ← R1 + 1, R3 ← R1 AND R2.
11. Memory & Error Correction
1. How many locations can 12 address lines select?
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4096
2. Calculate the capacity of a 2K × 8 memory.
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16384 bits, which is 2 KB.
3. Explain address decoding.
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A decoder converts the address bits into one select line, which activates the addressed location or chip.
4. Design a 3-to-8 decoder-based selection system.
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The top three address bits drive a 3-to-8 decoder. Each output is the chip select of one of eight memory chips.
5. Distinguish word expansion from bit expansion.
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Word expansion increases the number of locations and needs decoding. Bit expansion widens the word by putting chips in parallel.
12. ROM & Programmable Logic
1. Explain ROM organization.
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Address lines feed a decoder. Each decoder output selects one stored word, and the OR gates present that word’s bits at the outputs.
2. Compare PROM, EPROM, EEPROM and Flash.
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PROM: programmed once. EPROM: UV erase. EEPROM: electrical erase by byte. Flash: electrical erase in blocks.
3. Describe the PLA architecture.
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Inputs and their complements feed a programmable AND array (product terms), which feeds a programmable OR array (outputs).
4. Compare PLA and PAL.
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PLA: both arrays programmable. PAL: only the AND array is programmable.
5. Implement F = AB + A′C with programmable logic.
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Two product terms, AB and A′C, both connected to the OR gate of the output.
13. Digital Systems & Practice
1. Design a 3×3 multiplier.
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Generate nine partial products with AND gates, then add the shifted rows with half and full adders. See the multiplier on the Projects page.
2. Design an FSM that detects 101.
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Use the Chapter 8 simulator for the table and equations.
3. Design a MOD-6 counter.
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3 flip-flops, states 000 to 101, reset on 110 or use next-state logic.
4. List the blocks in a mini digital system.
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Input switches, combinational logic, a register, a counter, display logic and a control FSM.