Topic 6 of 13

Decoders, Encoders & Data Selectors

Circuits that route and select data: decoders, encoders, multiplexers and demultiplexers.

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Before we start

Why this matters

How does one skinny TV cable smuggle in a hundred channels at once, and how does your remote pick exactly one without opening the wall to check?

The cable is basically shouting every channel at the same time; a multiplexer inside the TV politely tells 99 of them to be quiet and listens to just one. Your remote does the reverse trick, squashing “channel 214” into a couple of button presses. Decoders, encoders and multiplexers are the bouncers of digital design — today you build the velvet rope.

Outline

Topics in this chapter

Select a topic to jump to the slide that explains it.

2-to-4 and 3-to-8 decoders
Enable and decoder combinations
Decoder-based circuit design
4-to-2 and octal-to-binary encoders
Priority encoder
2-to-1 and 4-to-1 multiplexers
Boolean function implementation using MUX
1×4 and 1×8 demultiplexers
Decoder vs. encoder
MUX vs. DEMUX
Applications

Concept 1 of 4

Decoders

A and B pick which single output line goes active; EN (orange) switches the whole decoder on or off.

An n-to-2ⁿ decoder turns an n-bit code into one active output line. Each output is a minterm of the inputs. For a 2-to-4 decoder: Y0 = A′B′, Y1 = A′B, Y2 = AB′, Y3 = AB.

Explore furtherInside the Computer74LS138 chip (3-to-8 decoder)Gate Forge2-to-4 DecoderProblems › Encoders & Decoders Gate Forge3-to-8 DecoderProblems › Encoders & Decoders

Concept 1 of 4

Decoders (cont.)

An enable input switches the whole decoder on or off. Enable lets you build big decoders from small ones: a 3-to-8 decoder is two 2-to-4 decoders, with the third input bit driving the enables. Since a decoder makes every minterm, any function is an OR of its output lines. A full adder needs one 3-to-8 decoder and two OR gates. Decoders also drive memory address selection and displays.

OR-ing minterms isn’t always the cheapest option. If a function F has k minterms and k is more than half of 2ⁿ, its complement F′ has only 2ⁿ − k minterms — fewer decoder lines to combine. Since F = (F′)′, a single NOR gate fed by F′’s minterm lines produces F directly, which is cheaper than an OR gate with more inputs.

F′ = sum of the minterms NOT in F (there are 2ⁿ − k of them)
F = NOR(those D_i lines) — cheaper than OR(F’s own k minterms) when k > 2ⁿ/2

Concept 1 of 4

Decoders (cont.)

2-to-4 decoder with enable

E	A	B	Y0	Y1	Y2	Y3
0	0	0	0	0	0	0
0	0	1	0	0	0	0
0	1	0	0	0	0	0
0	1	1	0	0	0	0
1	0	0	1	0	0	0
1	0	1	0	1	0	0
1	1	0	0	0	1	0
1	1	1	0	0	0	1

Interactive circuit

2-to-4 decoder

Click the switches to change the inputs and watch the LEDs. Use “Show truth table” when it appears.

Concept 2 of 4

Encoders

Exactly one active D line becomes the code A B. V (orange, dashed) only exists on a priority encoder — it flags whether any input is active at all.

An encoder does the reverse: one active input becomes a binary code. A 4-to-2 encoder has A = D2 + D3 and B = D1 + D3. An octal-to-binary encoder has A2 = D4+D5+D6+D7, A1 = D2+D3+D6+D7, A0 = D1+D3+D5+D7.

A basic encoder assumes only one input is active. A priority encoder allows several and outputs the code of the highest-priority one, plus a valid flag V that says whether any input is active.

Explore furtherGate Forge4-to-2 Priority EncoderProblems › Encoders & Decoders Gate ForgeElevator Call Button Priority EncoderProblems › Encoders & Decoders

Concept 2 of 4

Encoders (cont.)

A basic encoder has a blind spot even when its one-active-input rule is obeyed: with no valid flag, “D0 is the only active input” and “no input is active” both produce the same code 00 — the circuit can’t tell them apart. It can also misbehave if the one-active-input rule is broken: if D3 and D6 were both 1 at once, a 4-to-2 encoder would output 11 (from A) and 1 (mis-OR’d elsewhere), and an octal encoder would output 111, which is neither 3 nor 6. A priority encoder’s V bit and priority logic resolve both problems at once.

4-to-2 encoder (one input active)

D3	D2	D1	D0	A	B
0	0	0	1	0	0
0	0	1	0	0	1
0	1	0	0	1	0
1	0	0	0	1	1

4-input priority encoder

D3	D2	D1	D0	A	B	V
0	0	0	0	X	X	0
0	0	0	1	0	0	1
0	0	1	X	0	1	1
0	1	X	X	1	0	1
1	X	X	X	1	1	1

X means don’t care. The highest-priority active input wins.

Interactive circuit

4-to-2 priority encoder

D3 has the highest priority. A1 = D3+D2, A0 = D3+D2′D1, and V = D0+D1+D2+D3. Click the switches — try turning on more than one input and see which one wins.

Concept 3 of 4

Multiplexers

Data inputs I0–I3 arrive on the left; the select lines S1 S0 (orange, entering from below) choose which one reaches Y.

A multiplexer (MUX) is a data selector: 2ⁿ data inputs, n select lines and one output.

Explore furtherInside the ComputerMultiplexer Inside the Computer74LS157 chip (2-to-1 MUX)Inside the Computer74LS151 chip (8-to-1 MUX)Gate Forge2x1 MultiplexerProblems › Multiplexers Gate Forge4x1 MultiplexerProblems › Multiplexers

Concept 3 of 4

Multiplexers (cont.)

2-to-1: Y = S′·I0 + S·I1
4-to-1: Y = S1′S0′I0 + S1′S0 I1 + S1 S0′ I2 + S1 S0 I3

A MUX can generate any function. Feed n−1 of the variables to the select lines and connect each data input to 0, 1, the last variable, or its complement.

Several 1-bit MUXes can share one set of select lines to switch a whole bus at once. A quadruple 2-to-1 MUX is four 2-to-1 MUXes with a common select S: S=0 makes every Y_i = A_i, S=1 makes every Y_i = B_i, so a single control line swaps an entire 4-bit bus A for a 4-bit bus B. A shared enable E overrides S and forces every Y_i to 0 when the circuit is disabled.

Concept 3 of 4

Multiplexers (cont.)

2-to-1 multiplexer

S	I0	I1	Y
0	0	0	0
0	0	1	0
0	1	0	1
0	1	1	1
1	0	0	0
1	0	1	1
1	1	0	0
1	1	1	1

4-to-1 multiplexer

S1	S0	Y
0	0	I0
0	1	I1
1	0	I2
1	1	I3

Quadruple 2-to-1 MUX (function table)

E	S	Output Y
1	X	all 0’s
0	0	select A
0	1	select B

Interactive circuit

2-to-1 multiplexer

Click the switches to change the inputs and watch the LEDs. Use “Show truth table” when it appears.

Concept 4 of 4

Demultiplexers

The single data line D is routed to exactly one of Y0–Y3, chosen by the select lines S1 S0 — the mirror image of a multiplexer.

A demultiplexer (DEMUX) sends one input to one of 2ⁿ outputs chosen by the select lines. A decoder with an enable input works as a DEMUX: use the enable as the data input. A 1×8 DEMUX can be built from a 1×2 DEMUX in front of two 1×4 DEMUXes, with the top select bit choosing which 1×4 receives the data.

Explore furtherGate Forge1x2 DemultiplexerProblems › Demultiplexers Gate Forge1x4 DemultiplexerProblems › Demultiplexers

Concept 4 of 4

Demultiplexers (cont.)

1×4 demux (I = data, S1 S0 = select):
Y3 = S1 S0 I Y2 = S1 S0′ I Y1 = S1′ S0 I Y0 = S1′ S0′ I

Decoder	Encoder	MUX	DEMUX
Code → one line	One line → code	Many inputs → one output	One input → many outputs

1×4 demultiplexer

S1	S0	Y0	Y1	Y2	Y3
0	0	D	0	0	0
0	1	0	D	0	0
1	0	0	0	D	0
1	1	0	0	0	D

Interactive

Demo: decoder, encoder, MUX and DEMUX

Worked example 1 of 4

Worked example 1

Implement F(A,B,C) = Σm(1,2,6,7) with a 4-to-1 MUX (A and B on the select lines).

Show the solution

AB = 00: F = 0 when C = 0 and 1 when C = 1, so I0 = C.
AB = 01: F = 1 when C = 0 and 0 when C = 1, so I1 = C′.
AB = 10: F = 0 for both, so I2 = 0.
AB = 11: F = 1 for both, so I3 = 1.

Worked example 2 of 4

Worked example 2

Build a 3-to-8 decoder from two 2-to-4 decoders.

Show the solution

Connect B and C to both decoders’ inputs.
Drive the enable of the first with A′ (outputs Y0–Y3) and of the second with A (outputs Y4–Y7).

Worked example 3 of 4

Worked example 3

Implement G(x,y,z) = Σm(0,1,2,3,4,5,6) using a 3-to-8 decoder. Is it cheaper to OR the minterms of G, or to build G through its complement?

Show the solution

G has k = 7 minterms out of 2³ = 8, and 7 > 8/2, so building G directly means OR-ing 7 decoder output lines.
G′ has 2³ − 7 = 1 minterm: only m7 (D7 = xyz) is missing from G.
Since G = (G′)′ and G′ = D7, a single NOR of one line — which is just an inverter on D7 — gives G directly: G = D7′.

Result G = D7′, built with one inverter instead of a 7-input OR gate.

Worked example 4 of 4

Worked example 4

Build a 1-to-8 demultiplexer from one 1-to-2 demultiplexer and two 1-to-4 demultiplexers, with data input I and select lines s2 s1 s0.

Show the solution

Feed I into the 1-to-2 demux, selected by s2; its two outputs become the data inputs of the two 1-to-4 demuxes.
Give both 1-to-4 demuxes the same select lines s1 and s0.
When s2 = 0, only the lower 1-to-4 demux is fed I, and it routes I to one of Y0–Y3 based on s1 s0 (the upper one outputs all 0s).
When s2 = 1, only the upper 1-to-4 demux is fed I, routing it to one of Y4–Y7 based on s1 s0.

Result: I appears on exactly one of Y0–Y7, chosen by s2 s1 s0.

Practice

Practice (1 of 2)

Try each one on paper first, then check your answer.

1. Design a 2-to-4 decoder.

Show the answer

Y0 = A′B′, Y1 = A′B, Y2 = AB′, Y3 = AB (four AND gates and two inverters).

2. Design a 4-to-2 encoder.

Show the answer

A = D2 + D3, B = D1 + D3 (assuming one active input).

3. Write the equation of a 2-to-1 MUX.

Show the answer

Y = S′·I0 + S·I1

Practice

Practice (2 of 2)

Try each one on paper first, then check your answer.

4. Explain priority encoding.

Show the answer

When several inputs are 1, the encoder outputs the code of the highest-priority one, and a valid bit shows whether any input is active.

5. Compare MUX and DEMUX.

Show the answer

MUX selects one of many inputs for one output. DEMUX routes one input to one of many outputs.

Practice in Gate Forge

Build a 2-to-4 decoder and a 4-to-1 multiplexer, then run the Truth table tester on them.

Open Gate Forge

Gate ForgeA free circuit simulator — place and wire gates, generate truth tables and timing diagrams, and work through 90+ guided problems.

Check yourself

Quiz

Summary

A decoder makes all minterms of its inputs.
An encoder is the reverse. Priority encoders resolve multiple active inputs.
A MUX is a data selector. 2-to-1: Y = S′I0 + S·I1.
Any function fits a MUX with data inputs from {0, 1, X, X′}.
A decoder with enable is a DEMUX.

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