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Topic 9 of 13

Counters

Ripple, synchronous, up/down, MOD-N, ring and Johnson counters, and frequency division.

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Before we start

Why this matters

What's actually ticking inside a digital clock, and why does a car's odometer roll from 099999 to 100000 instead of just giving up?

A chain of flip-flops, each one flipping its neighbour the instant it overflows — the exact same domino effect as your car's odometer wheels nudging each other along. Wire it one way and you get a clock or a scoreboard; wire it backwards and you get a very confusing countdown to a party that already happened.

Outline

Topics in this chapter

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  1. Counter fundamentals
  2. Binary counters
  3. Asynchronous/ripple counters
  4. Wiring rule: Q vs Q′ to the next clock
  5. Synchronous counters
  6. Up/down counters
  7. MOD-N counters
  8. MOD-6, MOD-8, MOD-10, MOD-14, MOD-16
  9. Truncated counters
  10. Counter reset
  11. Flip-flop requirements
  12. Ring counters
  13. Johnson counters
  14. Frequency division
  15. Counter applications

Concept 1 of 6

Counter basics

A counter is a set of flip-flops that steps through a fixed sequence of states. An n-bit binary counter has 2n states. A MOD-N counter has N states. Counters count events, measure time, divide frequency and sequence control logic.

Explore furtherInside the Computer74LS161 chip (4-bit counter)Gate Forge2-bit Counter (Next-State Logic)Problems › Counters

Concept 2 of 6

Ripple counters

In a ripple (asynchronous) counter, each flip-flop’s output clocks the next one. With T = 1 the first flip-flop toggles on every clock, the next on every other, and so on. Which output feeds the next stage's clock — and in which direction the count runs — depends on the flip-flop's active edge:

Wiring rule for the next stage's clock input

Active edgeFeed next CLK fromDirection
Negative (falling)QUp
Negative (falling)Q′Down
Positive (rising)Q′Up
Positive (rising)QDown

Either way, the rule is the same underlying idea: the next stage must see a falling edge (its own active edge, mirrored) exactly when the current stage rolls over in the counting direction you want.

Concept 2 of 6

Ripple counters (cont.)

Simple and cheap, but delay accumulates stage by stage, so intermediate states appear briefly and high speed is difficult. The maximum count of an n-bit counter is 2n − 1, since it starts at 0.

ClockQ0Q1Q23 × t_pd
Q0 toggles shortly after every clock edge, Q1 toggles shortly after Q0 falls, and Q2 shortly after Q1 falls — the same propagation delay is paid again at each stage (3 × t_pd by the third), which is why the dashed clock-edge lines drift out of alignment with each bit's own transition as the count 000…111…000 ripples through.

Interactive circuit

3-bit ripple counter (T flip-flops)

Click the switches to change the inputs and watch the LEDs. Use “Show truth table” when it appears.

Concept 3 of 6

Synchronous counters

All flip-flops share one clock, so state changes happen together. Gates decide which flip-flops toggle. For an up counter with T flip-flops: T0 = 1, T1 = Q0, T2 = Q0·Q1, T3 = Q0·Q1·Q2. Synchronous counters are faster than ripple counters and use more gates.

Explore furtherInside the Computer74LS161 chip (4-bit counter)Gate Forge4-bit Counter (Next-State Logic)Problems › Counters

Interactive circuit

3-bit synchronous counter

Click the switches to change the inputs and watch the LEDs. Use “Show truth table” when it appears.

Interactive circuit

3-bit synchronous counter (cont.)

Concept 4 of 6

Up/down counters

An up/down (bidirectional) counter steps through its sequence in either direction from a single control line, usually called UP/DOWN (HIGH = count up, LOW = count down). Bit 0 always toggles on every clock. A higher bit toggles exactly when every bit below it is 1 while counting up, or every bit below it is 0 while counting down — the control input just selects which of those two conditions is live:

J0 = K0 = 1
J1 = K1 = (Q0·UP) + (Q0′·DOWN)
J2 = K2 = (Q0·Q1·UP) + (Q0′·Q1′·DOWN)

The same pattern extends to any higher stage: AND the "all lower bits are 1" term with UP, AND the "all lower bits are 0" term with DOWN, then OR the two together.

Concept 4 of 6

Up/down counters (cont.)

FF0FF1FF2ToggleselectToggleselectJKQ0JKQ1JKQ2Q0Q0′Q1Q1′Q2UPDOWN
Block view of a 3-bit up/down synchronous counter: between each pair of stages, a toggle-select block chooses the Q·UP condition or the Q′·DOWN condition and drives both J and K of the next flip-flop with it, so the same hardware counts in either direction depending on which bus is HIGH.

Concept 4 of 6

Up/down counters (cont.)

3-bit up/down sequence

ClockUpQ2Q1Q0Down
0↗000↙
1↗001↙
2↗010↙
3↗011↙
4↗100↙
5↗101↙
6↗110↙
7↗111↙

Read the Up column top-to-bottom (0→7) to count up, or the Down column bottom-to-top (7→0) to count down — it is the same 8-state cycle run in each direction.

Concept 5 of 6

MOD-N and truncated counters

Choose n so that 2n ≥ N. A MOD-10 (decade) counter needs 4 flip-flops and skips six of the 16 states, so it is truncated. A MOD-6 counter counts 000 to 101 then resets. Truncation is done by detecting state N and resetting (asynchronously or synchronously) or by designing the next-state logic directly. A reset forces a known start state, usually all zeros.

Explore furtherGate ForgeDecade Counter (Mod-10, Next-State Logic)Problems › CountersGate ForgeMod-6 Counter using D Flip-FlopProblems › Counters

Concept 6 of 6

Ring and Johnson counters; frequency division

A ring counter circulates a single 1 through a shift register (1000 → 0100 → 0010 → 0001), giving n states from n flip-flops. A Johnson counter feeds the complement of the last output back to the first, giving 2n states.

Frequency division: the output of stage k of a binary counter has frequency f/2k+1. A MOD-N counter’s last output is f/N.

Explore furtherInside the Computer74LS194 chip (shift register)Inside the ComputerClock

Interactive circuit

Divide-by-2 (D flip-flop, Q′ to D)

Click the switches to change the inputs and watch the LEDs. Use “Show truth table” when it appears.

Truth tables

Truth tables (1 of 3)

3-bit up counter with T flip-flops

Q2Q1Q0T2 = Q1Q0T1 = Q0T0Next
000001001
001011010
010001011
011111100
100001101
101011110
110001111
111111000

Truth tables

Truth tables (2 of 3)

MOD-6 counter

CountQ2Q1Q0Next
0000001
1001010
2010011
3011100
4100101
5101000
6110unused
7111unused

States 110 and 111 are never used. Reset at 110 (or design the next-state logic) makes the count return to 000.

4-bit ring counter

ClockQ3Q2Q1Q0
01000
10100
20010
30001
41000

Truth tables

Truth tables (3 of 3)

4-bit Johnson counter

ClockQ3Q2Q1Q0
00000
11000
21100
31110
41111
50111
60011
70001
80000

Interactive

Demo: live counters

Worked example 1 of 7

Worked example 1

How many flip-flops does a MOD-12 counter need?
Show the solution
  1. 23 = 8 < 12 ≤ 16 = 24.
  2. 4 flip-flops.

Worked example 2 of 7

Worked example 2

A 16 kHz clock drives a 4-bit binary counter. What is the frequency of Q3?
Show the solution
  1. Q3 divides by 24 = 16.
  2. 16 kHz / 16 = 1 kHz.

Worked example 3 of 7

Worked example 3

Give the state sequence of a MOD-6 counter.
Show the solution
000 → 001 → 010 → 011 → 100 → 101 → 000. States 110 and 111 are unused.

Worked example 4 of 7

Worked example 4

Each J-K flip-flop in a 4-bit ripple (asynchronous) counter has a propagation delay of 15 ns. What is the worst-case time for the count to settle after a clock edge, and how does a synchronous counter compare?
Show the solution
  1. In a ripple counter each stage is clocked by the previous stage's output, so a change has to propagate stage by stage. The worst case is a transition where every stage toggles (e.g. 0111 → 1000).
  2. Worst-case settle time = n × tpd = 4 × 15 ns = 60 ns.
  3. In a synchronous counter every flip-flop is driven directly by the same clock, so only one flip-flop's delay (15 ns) separates the clock edge from the outputs settling, no matter how many bits.
Result: 60 ns for the ripple counter vs 15 ns for the synchronous counter. This accumulated delay is also why a ripple counter's outputs pass briefly through incorrect intermediate states ("glitches") while the count ripples through.

Worked example 5 of 7

Worked example 5

Design an asynchronous MOD-6 counter with J-K flip-flops that counts 0 to 5 then resets. How many flip-flops are needed, which state must be detected, and how is the reset wired?
Show the solution
  1. 22 = 4 < 6 ≤ 8 = 23, so 3 flip-flops are needed (states 000–111; 110 and 111 are unused).
  2. Wire the three flip-flops as an ordinary 3-bit binary (ripple or synchronous) up counter.
  3. The count must be forced back to 000 as soon as it reaches 110 (state 6): feed Q2 and Q1 into a NAND gate and connect the NAND output to the asynchronous CLR input of every flip-flop.
  4. The counter reaches 110 for only a few nanoseconds before the NAND output clears it to 000, so 110 and 111 never appear as stable states in the output sequence.
Result: 3 flip-flops, with Q2·Q1 decoded by a NAND gate wired to CLR.
000001010011100101110unused111unusedresetQ2Q1 detectedby NAND, cleared
State diagram of the design: the counter cycles 000→001→010→011→100→101→000, with the last step being the engineered reset rather than a natural binary rollover. States 110 and 111 are reachable only for the instant the NAND gate takes to clear them, so they never persist.

Worked example 6 of 7

Worked example 6

A synchronous up/down counter has a control line UP/DOWN (HIGH = count up, LOW = count down). Find J1 = K1 for the second stage (Q1).
Show the solution
  1. Counting up, Q1 changes state on the next clock exactly when Q0 = 1 (the same condition as a plain up counter).
  2. Counting down, Q1 changes state on the next clock exactly when Q0 = 0 (a "borrow" out of the LSB).
  3. Combine both conditions through the control input.
Result: J1 = K1 = (Q0·UP) + (Q0′·DOWN). The same pattern extends to every higher stage, e.g. J2 = K2 = (Q0Q1·UP) + (Q0′Q1′·DOWN).

Worked example 7 of 7

Worked example 7

A 3-bit synchronous up/down counter starts at 000. The UP/DOWN control is HIGH (count up) for the first 3 clock pulses, then LOW (count down) for the next 2. What is the state after each pulse?
Show the solution
  1. Start: 000.
  2. Pulse 1 (UP): 000 → 001.
  3. Pulse 2 (UP): 001 → 010.
  4. Pulse 3 (UP): 010 → 011.
  5. Pulse 4 (DOWN): 011 → 010.
  6. Pulse 5 (DOWN): 010 → 001.
Result: the counter passes through 000 → 001 → 010 → 011 → 010 → 001, climbing for the first 3 pulses and retracing its own steps once UP/DOWN goes low — exactly as if it had simply reversed direction on the same 3-bit odometer.

Practice

Practice (1 of 2)

Try each one on paper first, then check your answer.

1. Design a 3-bit ripple counter.
Show the answer
Three T flip-flops with T = 1. Clock the first, and connect Q′ of each stage to the clock of the next (for positive-edge flip-flops). Try the circuit below.
2. Compare ripple and synchronous counters.
Show the answer
Ripple: clock passes stage to stage, simple, accumulating delay. Synchronous: common clock, faster, needs extra gates.
3. Design an up/down counter.
Show the answer
Add a control input. For stage k use Tk = (Q0·…·Qk−1)·UP + (Q0′·…·Qk−1′)·DOWN, with T0 = 1.

Practice

Practice (2 of 2)

Try each one on paper first, then check your answer.

4. How many flip-flops for a MOD-12 counter?
Show the answer
4
5. Explain ring and Johnson counters.
Show the answer
A ring counter circulates one 1 (n states). A Johnson counter feeds back the complement of the last stage (2n states).
Practice in Gate Forge

Build a 3-bit ripple counter and a MOD-6 counter with a Clock, and read the Timing diagram.

Open Gate ForgeGate ForgeA free circuit simulator — place and wire gates, generate truth tables and timing diagrams, and work through 90+ guided problems.

Check yourself

Quiz

Summary

Summary

  • n flip-flops give 2n states. MOD-N needs 2n ≥ N.
  • Ripple counters are simple but slow. Synchronous counters share one clock.
  • Truncated counters skip states by reset or by design.
  • Ring: n states. Johnson: 2n states.
  • A binary counter stage k divides the clock by 2k+1.
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